Current Project

This is a collaborated work with Professor Lei Wang and his student Shuo Wang. The motivation is to use the memory techniques to defeat power analysis attacks and faulty analysis on the cryptographic algorithm implementations.

Group members: Z. J. Shi, F. Zhang (CSE) and L. Wang, S. Wang (ECE)

References:

[Register Renaming]

1.      General purpose register renaming. [PDF]

2.      Power-aware register renaming, Technical report by Andreas Moshovos. [PDF]

3.      X. Qian, H. Huang, Z. Duan, J. Zhang, N. Yuan, Y. Zhou, H. Zhang, H. Cui, and D. Fan,  “Optimized register renaming scheme for stack-based x86 operations,” Architecture of Computing Systems: ARCS 2007,  LNCS, vol. 4415, pp. 43-56, 2007. [PDF]

4.      T. N Buti, R. G. McDonald, Z. Khwaja, A. Ambekar, H. Q Le, W. E. Burky, and B. Williams, “Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors, ” IBM J. Research and Development, vol. 49, no. 1, pp. 167-188, Jan. 2005. [PDF]

5.      B. Bishop, T. P Kelliher, and M. J. Irwin, “The design of a register renaming unit,” Proceeding. of Ninth Great Lakes Symposium on VLSI,  pp.34-37, 1999. [PDF]

6.      D. May, H. L. Muller, and N.P. Smart, “Random register renaming to foil DPA,” Cryptographic hardware and embedded systems-CHES 2001, pp. 28-38, 2001. [PDF]

7.      G. Kucuk, O. Ergin, D. Ponomarev, and K. Ghose, “Energy efficient register renaming,” Integrated Circuit and System Design, LNCS, vol. 2799, pp. 219-228, 2003. [PDF]

8.      D. Sima, “The design space of register renaming techniques in superscalar processors, ” IEEE MICRO, pp. 70-83, 2000. [PDF]

9.      T. Monreal, A. Gonzalez, M. Valero, J. Gonzalez, and V. Vinals, “Dynamic register renaming through virtual-physical registers,” Journal of Instruction Level Parallelism, 2000. [PDF]

[Differential Power Analysis]

1.      M. Alioto, M, Poli, and, S. Rocchi, “A general power model of differential power analysis attacks to static logic circuits,” Transactions on Very Large Scale Integration (VLSI) Systems: TVLSI, 2008. [PDF]

2.      P. Kocher, J. Jaffe, and B. Jun, “Differential power analysis,” Proceedings of CRYPTO'99, vol. 1666, pp. 388-397, August 1999. [PDF]

3.      J. S. Coron, “Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems,” Proceedings of CHES'99, August 1999. [PDF]

4.      T. S. Messerges, E. A. Dabbish, and R. H. Sloan, “Examining smart-card security under the threat of power analysis attacks,” IEEE Transactions on Computers, vol. 51, no. 5, pp. 541-552, May 2002. [PDF]

5.      T. S. Messerges, E. A. Dabbish, R. H. Sloan, “Power Analysis Attacks of Modular Exponentiation in Smartcards,” Cryptographic Hardware and Embedded Systems: First International Workshop, CHES'99, Worcester, MA, USA, August 1999. Proceedings [PDF]

6.      R. Muresan, H. Vahedi, Y. Zhanrong, S. Gregori, “Power-smart System-on-Chip architecture for embedded cryptosystems,” Proceedings of CODES+ISSS’05, pp. 184-189, September 2005. [PDF]

7.      K. Tiri, I. Verbauwhede, “Securing encryption algorithms against DPA at the logic level: next generation smart card technology,” Proceedings of CHES 2003, LNCS, vol. 2779, pp. 127-137, 2003. [PDF]

[Fault Analysis]

1.      E. Biham and A. Shamir, "Differential Fault Analysis on Secret Key Cryptosystems," Advances in Cryptology - CRYPTO '97: 17th Annual International Cryptology Conference, LNCS, pp. 513-525, vol. 1294, 1997[PDF]

2.      J. Blömer, and J. P. Seifert, "Fault Based Cryptanalysis of the Advanced Encryption Standard (AES)," FC 2004, Proceedings, LNCS, Vol. 2742, pp 162-181. [PDF]

3.      C. N. Chen, and S. M. Yen, "Differential Fault Analysis on AES Key Schedule and Some Coutermeasures," ACISP 2003, Proceedings, LNCS, Vol. 2727, pp. 118-129, 2003 [PDF]

[Other Papers]

1.      D. May, H. L. Muller, and N. P. Smart, “Non-deterministic processors,” Proceedings of ACISP 2001, LNCS, July 2001. [PDF]

2.      O. Kommerling and M. Kuhn, "Design principles for tamper-resistant smartcard processors," In Proc. of the usenix Workshop on Smartcard Technology (Smartcard’99), pp. 9-20. usenix Association, 1999. [PDF]

 [Papers from this group]

1.      L. Wang, “Improving error tolerance for multithreaded register files,” Transactions on Very Large Scale Integration (VLSI) Systems: TVLSI, 2007. [PDF]

2.      E. S. Fetzer, L. Wang, and J. Jones, “The multi-threaded, parity-protected128-word register files on a Dual-Core Itanium®-Family Processor,” ISSCC,  2005. [PDF]

3.      F. Zhang and Z. J. Shi, "An efficient window-based countermeasure to power analysis of ECC algorithms," accepted by Proceedings of ITNG 2008. [PDF]

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